The present invention relates in general to fabrication methods and resulting structures for semiconductor devices. More specifically, the present invention relates to fabrication methods and resulting structures for gate structures for nanosheet transistors having different work function metals and different nanosheet width dimensions.
In contemporary semiconductor device fabrication processes, a large number of semiconductor devices, such as n-type field effect transistors (nFETs) and p-type field effect transistors (pFETs), are fabricated on a single wafer. Non-planar transistor device architectures, such as nanosheet (or nanowire) transistors, can provide increased channel density and performance over planar transistors. In contrast to conventional planar FETs, nanosheet transistors include a gate stack that wraps around the full perimeter of multiple nanosheet channel regions for improved control of channel current flow. Nanosheet transistor configurations enable fuller depletion in the nanosheet channel regions and reduce short-channel effects.